1. Technical Field
The present invention relates to integrated circuits in general, and in particular to mutiport memory cell circuits. Still more particularly, the present invention relates to a single event upset hardened mutiport memory cell.
2. Description of the Prior Art
Multiport memories are random access memories that have multiple ports to enable parallel accesses, such as simultaneously reading a first memory location via a first port and writing a second memory location via a second port. Typically, multiport memories find their applications within integrated circuit devices as register files. A register file is a temporary buffer for storing intermediate results (and arguments) that are produced and used by various functional parts of an integrated circuit device, as it is well-known to those skilled in the relevant art.
In certain environments, such as satellite orbital space, in which the level of radiation is relatively intense, integrated circuit devices that utilize static random access memories (SRAMs) as memory cells for a storage element, such as a register file, are more susceptible to single event upsets (SEUs) or soft errors. These SEUs are typically caused by electron-hole pairs created by, and travelling along the path of, a single energetic particle as it passes through the SRAM cells. Should the energetic particle generate a critical charge within a storage node of an SRAM cell, the logic state of the SRAM cell will be upset, and erroneous results may be generated.